This invention relates generally to electrical circuits, and more particularly to comparators.
FIG. 1 illustrates a prior art comparator 1 for comparing an input voltage Vin with a reference voltage Vref and generating an output voltage Vout therefrom. Voltage Vin is applied to a voltage divider 2 comprising resistors R1, R2 and R3. Voltage divider 2 is coupled to provide a voltage VDIV to the gate of a transistor T1 via one of two switches SW1, SW2. When voltage VDIV exceeds reference voltage Vref, transistor T2 passes more current than transistor T1, the voltage at node 5 exceeds the voltage at node 4, and output voltage Vout is high. When voltage Vref exceeds voltage VDIV, transistor T1 passes more current than transistor T2, the voltage at node 4 exceeds the voltage at node 5, and voltage Vout is low.
As mentioned above, voltage VDIV is established by series-coupled resistors R1, R2 and R3 and switches SW1, SW2. Switches SW1 and SW2 are controlled to vary voltage VDIV such that comparator 1 exhibits hysteresis.